The present invention relates to a concept for reducing leakage currents of integrated circuits having at least one transistor, such as it can be used, for example, for reducing leakage currents in SRAM memory devices (SRAM=static random access memory).
Suppression or reduction, respectively, of leakage currents in integrated circuits is necessary to keep the power consumption of integrated circuits, such as SRAM memory devices, low. Power consumption by leakage currents can be substantially reduced by applying a technique known as “source biasing” in the art. This rises a potential at the source terminal of a transistor, wherein the bulk voltage remains on a reference potential or a ground potential, respectively. The power consumption by leakage currents can significantly influence the whole power consumption of a system and thus determine the life time of batteries, such as in mobile phones or PDAs (PDA=personal digital assistant).
Examples for integrated circuits are, for example, SRAM memory devices, which contribute disproportionately to leakage currents of integrated circuits due to their structure, particularly the NMOS and PMOS transistors found therein.
When an SRAM memory module is not accessed, for example in an energy-saving mode, the SRAM memory module has to be supplied with a data retention voltage, so that data stored in the memory module will not get lost. Thereby, the data retention voltage is normally the minimum required difference between a supply voltage VDD and the reference potential or ground potential VSS, respectively, of an integrated circuit, to retain stored data of the integrated circuit. If the applied data retention voltage of the SPAM memory device is above a minimum required value, power dissipation by leakage currents, for example of drain terminals to source terminals of MOS transistors of the SRAM memory cell is unnecessarily high. If, however, the data retention voltage of the SRAM memory cell sinks below the minimum required value, the risk of data loss increases.
One possibility for reducing leaking currents of integrated circuits is, for example, to use a so-called virtual ground or a virtual ground potential, respectively, when the respective integrated circuit is not accessed (“sleep mode”). Typically, integrated circuits are connected between a supply potential VDD and a reference potential or ground potential VSS, respectively. If the integrated circuit is not accessed in a sleep mode, a fixed virtual ground potential VSS,virt is used, which is, in amount, between the ground potential VSS and the supply potential VDD. Thereby, due to a lower difference of supply potential VDD and virtual ground potential VSS,virt, compared to the difference of supply potential VDD and actual ground potential VSS, lower leakage currents of the transistors of an integrated circuit result.
The fixed virtual ground potential VSS,virt has the disadvantage that with the same, a transistor circuit is not robust to variations of the supply voltage or operating voltage VDD, respectively. Variations of the supply voltage VDD are, for example, caused by a weak or pulsating energy supply, respectively. If the supply voltage VDD sinks below a critical value VDD,min, the potential difference resulting from VDD,min and the virtual ground potential VSS,virt is no longer sufficient to guarantee data retention in the SRAM memory cell.